MOdel-based DEsign & Verification for Embedded Systems

MODEVES Transformation Engine (MTE)

We develop MODEVES Transformation Engine (MTE) in order to transform the high level models into SystemVerilog RTL, Timed Automata model, SystemVerilog Assertions and CTL assertions code. Currently, we provide source code of MTE for evaluation. However, we will also release it as an Eclipse plugin in near future. The main interface of MTE is given below.

MODEVES Transformation Engine


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Sample Case Studies :

Once SystemVerilog RTL, Timed Automata model, SystemVerilog Assertions and CTL assertions code has been generated through MTE, both Static as well as Dynamic Assertion Based Verification has been performed. Few details can be found Here

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