SVOCL-Based Modeling Methodology
Modeling Structural Aspects:
SysML Block Definition Diagram (BDD) has been proposed to specify structural aspects of embedded systems. Particularly, BDD flow ports have been used to represent SystemVerilog input, output and inout registers.UML enumeration can be used to represent corresponding SystemVerilog enumeration. Properties can be used to represent SytemVerilog integer, string, real and Boolean data types. Complete structure modeling guidelines will be uploaded in MODEVES deliverables after scientific publication.
Modeling Behavioral Aspects:
Modeling behavioral aspects of embedded systems is a crucial part of requirement specification. In MODEVES framework, we propose state machine diagram to specify the behavioral aspects. However, it is not possible to consider all state machine diagram concepts / constructs in transformation engine. Therefore, we select significant state machine constructs with certain restrictions to model system behavior, so that, corresponding SystemVerilog RTL code can be generated through MODEVES transformation engine. Complete behavioral modeling guidelines will be uploaded in MODEVES deliverables after scientific publication.
Representation of Constraints / Assertions through SVOCL :
In MODEVES project, we propose OCL temporal extension named SVOCL (SystemVerilog in Object Constraint Language) to represent SystemVerilog Assertions (SVA’s) at higher abstraction level. We first identify leading property specification techniques (e.g. CCSL, OCL, SysML Parametric diagram) and provide the platform of SVOCL. The details can be found in our scientific publication "Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering" , 7th International Conference on Information Science and Applications, 2016. Paper will be uploaded soon .
Subsequently, we extend OCL to manage past and future temporal dimensions which are mandatory to represent SVA’s. We are not including technical details of SVOCL and such details can be found in our scientific publication "Expressing Embedded Systems Verification Aspects at Higher Abstraction Level - SystemVerilog in Object Constraint Language (SVOCL)" , 10th IEEESYSCON 2016. Paper will be uploaded soon .
We develop SVOCL transformation engine to generate SystemVerilog Assertions code from model where constraints are represented through SVOCL. The details and download link can be found here
MODEVES Transformation Engine (MTE) :
We develop MTE to generate both SystemVerilog RTL and assertions code from model. The details and download link can be found here
Sample Case Study
We have presented the modeling methodology to capture structural aspects (SYSML BDD), behavioral aspects (State Machine / Activity) and properties / assertions through SVOCL. We are including the sample case study (Traffic lights controller) to demonstrate the application of MODEVES modeling methodology. This facilitates end users to understand the application of MODEVES modeling methodology in order to represent the structure, behavior and SystemVerilog Assertions at higher abstraction level. The details can be found here