MOdel-based DEsign & Verification for Safety-Critical Embedded Systems

MODEVES Project

The MODEVES project introduces a novel framework to support the model-based design verification of safety-critical embedded systems. The major features are:

1. A methodology to embed the verification constraints along with the structural and behavioral aspects of embedded systems at higher abstraction level

2. A transformation engine to automatically generate System Verilog Register Transfer Level (RTL) and SystemVerilog Assertions (SVAs)

3. Dynamic verification of embedded systems by using the automatically generated code through a UVM-compliance (Universal Verification Methodology) simulator

Overview

The early design verification of safety-critical embedded systems is a key research area due to the complexity of these systems. Model Based System Engineering (MBSE) ...........